Dr. AMIT SEHGAL

S/O Mr. K. C. Sehgal

D.O.B. : 01 – 12 – 1979

Tel. No. – 27565218 (R), 9873035542 (M)

Email : amitsehgal112@yahoo.com

URL: http://people.du.ac.in/~asehgal/

 

Address: D – 42, Prashant Vihar,

Rohini,

Delhi – 110085

 

9+ years of teaching experience at Delhi University

13+ years of research experience (Modeling of Semiconductor Devices)

With 28 publications produced in journals and conferences

 

EDUCATIONAL QUALIFICATIONS:

 

Course

Year

Board

/Univ.

Subjects

Specialization

%age

Division

Ph. D.

Jan. 2007

Delhi University

Electronic Science

Microelectronics

 

Passed

M. Sc.

2002

Delhi University

Electronics

Electronics

69.57%

First

B. Sc. (Hons)

2000

Delhi University

Electronics

Electronics

75.67%

First

10+2

1997

C.B.S.E.

Physics, Chemistry, Maths, English, Computer Sc.

 

76%

First

 

Thesis title “Poly–crystalline Silicon Thin Film Transistors: Modeling, Simulation and Characterization” is submitted to Univ. of Delhi.

Cleared UGC NET December 2002 Examination and qualified for both Junior Research Fellowship and Lectureship.

 

One Orientation Course attended and completed successfully in May – June, 2008

Two Refresher Courses attended and completed successfully

  • Research Methodology in December, 2011
  • Physics in September – October, 2013.

 

COMPUTER AND MICROPROCESSOR KNOWLEDGE:

  • Can operate computer efficiently in Windows, MS Office, Internet, MathCAD, Microsoft Origin, Adobe softwares viz. Acrobat Professional, Adobe Dreamweaver and Adobe Photoshop etc.
  • Can install Windows, Linux and Mac OS efficiently on Personal Computers and Laptops.
  • Can install any software on any operating system.
  • Installed XAMPP Server on Personal Computer and installed dummy MOODLE environment on that server.
  • Computer Languages known = FORTRAN, Pascal
  • Machine and Assembly Languages known = 8085, 8086
  • Have done programming on various simulators and emulators eg: ATLAS simulator, 8085 emulator, 8086 emulator, Microsoft Assembler MASM etc.
  • Contributed e-learning material in Physics subject as E-LABS on http://vle.du.ac.in education portal designed and developed by Institute of Life Long Learning, University of Delhi
  • Designed and developed personal and company websites eg: http://people.du.ac.in/~asehgal/ , http://drtinamangla.appspot.com and http://csakg.com

 

ACHIEVEMENTS:

  • Biography listed in Marquis Who's Who in World 25th Anniversary Edition issue.
  • Biography listed in Marquis Who's Who in Asia December 2006 issue.
  • Biography listed in Marquis Who's Who in Science and Engineering September 2006 issue.

 

MEMBERSHIPS:

·         SID (Society For Information Display) Member

·         Society of VLSI and Microelectronics Member

·         Material Research Society Singapore Member

 

EXPERIENCE:

Work Exposure

Name of the Post 

Nature of the Job

 

Duties

 

Name of Organization

 

Period

From

To

Assistant Professor

(Electronics)

Permanent

To teach undergraduate students

Hansraj College,

University of Delhi

01-01-06

Till date

Lecturer

(Electronics)

Permanent

To teach undergraduate students

Hansraj College,

University of Delhi

17-02-05

31-12-05

Visiting Faculty

(Computer Science)

Temporary

To teach undergraduate students

Sri Guru Gobind Singh College of Commerce, University of Delhi

08-01-10

Till date

Visiting Faculty

(Computer Science)

Temporary

To teach undergraduate students

Hansraj College,

University of Delhi

17-07-05

12-04-10

Visiting Faculty

(Computer Science)

Temporary

To teach undergraduate students

Shyama Prasad Mukherjee College, University of Delhi

12-12-08

27-03-09

Visiting Faculty

(Computer Science)

Temporary

To teach undergraduate students

Shyama Prasad Mukherjee College, University of Delhi

01-09-08

05-11-08

Visiting Faculty

(Computer Science)

Temporary

To teach undergraduate students

Indraprastha College  of Women, University of Delhi

09-01-07

26-04-07

UGC - JRF

Temporary

Research

Dept. of Elec. Sc., Univ. of Delhi (South Campus)

01-02-04

16-02-05

Project JRF

Temporary

Research

Dept. of Elec. Sc., Univ. of Delhi (South Campus)

12-02-03

31-01-04

 

Working on research topic “Modeling, Simulation & Characterization of Semiconductor Devices (especially poly-silicon Thin Film Transistor and Nano-scale MOSFETs)” with Prof. R. S. Gupta (supervisor) at Dept. of Elec. Sc., Univ. of Delhi (South Campus), N. Delhi -21.

 

Administrative Experience

Year 2014 – 2015

Member– Finance Committee 

Member– Music Society 

Convener– Departmental Students Society

Member– Departmental Purchase Committee 

Member– Departmental Administrative Committee 

Member– Departmental Infrastructural Development Committee

 

Year 2013 – 2014

Member– Finance Committee 

Member– Portal Committee 

Member– Department Workload Committee 

Member– Departmental Laboratory Infrastructural Development

Presiding Officer – Students Union Elections

 

Year 2012 – 2013

Member– Finance Committee 

Member – Seminar Committee 

Convener – Departmental Students Society 

Member– Departmental Laboratory Infrastructural Development

Presiding Officer – Students Union Elections 

 

Year 2011 – 2012

Secretary– Staff Association

Member– Portal Committee 

Member – Seminar Committee 

Presiding Officer – Students Union Elections

 

Year 2010 – 2011

ON DEPUTATION Fellow– Physics 

 

Year 2009 – 2010

Member– Finance Committee 

Member – Canteen Committee 

Member – Portal Committee 

Convener – Admission Committee (for 2nd cut-off list admissions) 

Member– Departmental Purchase Committee 

Member– Departmental Infrastructural Development Committee

Presiding Officer – Students Union Elections 

 

Year 2008 – 2009

Member – Admission Committee & B.Sc. (Honors) Electronics Admission In-charge

Member – Canteen Committee

Member – Portal Committee

Convener – Department Student Society

Member   Departmental Purchase Committee

Presiding Officer – Students Union Elections

     

Year 2007 - 2008

Convener – Student Welfare Committee

Member – Finance Committee

Member – Portal Committee

Convener – Departmental Purchase Committee

Member – Department Time Table Workload Committee

Presiding Officer – Students Union Elections

     

Year 2006 - 2007

Member – Student Welfare Committee

Member – Departmental Purchase Committee

 

Research Experience

Published 26 research articles in international/national journals and conferences. (List of Publications in Appendix A)

Doing research work on topics

·         “Modeling, Simulation & Characterization of Short Geometry Poly-silicon Thin Film Transistor”

·         “Modeling, Simulation & Characterization of MOSFETs with quantum mechanical effects for ULSI applications”

from September, 2002 onwards till date.

 

Projects

·         Working on project titled “Designing and Optimization of Auto-Tracking Solar Energy based Energy Conversion Module for Rechargeable Appliances” as project investigator under Innovation Project Scheme, University of Delhi.

·         Completed project titled “Fabrication of Porous Silicon and Study of its Resistive Behavior under different Environmental Conditions” for the partial fulfillment of award of degree of M. Sc. in Electronics under guidance of Dr. V. K. Jain (Add. Director / Scientist G SSPL) and Prof. R. M. Mehra (Univ. of Delhi) at Solid State Physics Laboratory, Ministry of Defence, Timar Pur, New Delhi.

·         Completed project titled “Designing and Testing of Successive Approximation Digital Voltmeter by interfacing with 8085 Microprocessor Kit” for the partial fulfillment of award of degree of B. Sc. (Hons) Electronics at Electronics Laboratory, Keshav Mahavidyalaya, University of Delhi, Keshav Puram, New Delhi.

·         Designed software based project titled “Telephone Billing in Pascal Programming” for the award of 10+2 passing certificate.   

 

 

 

(AMIT SEHGAL)

Appendix A

 

List of Publications

International/Indian Journals

Published

  1. “Optimization of gate stack MOSFETs with quantization effects”, Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Technology and Science, Vol.4, No.3, September 2004, pp. 228-239.
  2. “Temperature dependence on electrical characteristics of short geometry poly – crystalline silicon thin film transistor”, Amit Sehgal, Tina Mangla, Mridula Gupta and R. S. Gupta, Solid State Electronics, Vol.49, No.3, March 2005, pp. 301-309.
  3. “Sub threshold analysis and drain current modeling of poly-silicon thin film transistor using green’s function approach” Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, IEEE Transactions on Microwave Theory  and Techniques, Vol.53, No. 9, September 2005, pp. 2682-2687.
  4. “Physics-based algorithm implementation for characterization of gate-dielectric engineered MOSFETs including Quantization effects”, Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Technology and Science, Vol.5, No.3, September 2005, pp. 159-167.
  5. “Physics based threshold voltage extraction and simulation for poly-crystalline thin film transistors using a double-gate structure”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol.21, March 2006, pp.370-377.
  6. “Enhancement in performance of poly-crystalline thin film transistors with gate dielectric and work-function”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, Thin Solid Films, Vo1.54, No.1-2, 2006, pp. 55-58.
  7. “Analytical modeling of the kink regime of a short channel polycrystalline silicon thin film transistor”, Sonia Chopra, Amit Sehgal and R. S. Gupta, International Journal of Electronics, Vol.93, No.5, May 2006, pp. 279-289.
  8. “Enhancement in performance of sub-100nm MOSFETs using gate stack architecture”, Tina Mangla, Amit Sehgal, Mridula Gupta and R. S. Gupta, International Journal on Microwave and Optical Technologies, Vol.1, No.1, June 2006, pp. 106-113.
  9. “Modeling and simulation of poly-crystalline silicon thin film transistor for improved gate transport efficiency”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, International Journal on Microwave and Optical Technologies, Vol.1, No.2, August 2006, pp. 411-416.
  10. “Modeling challenges in sub-100nm gate stack MOSFETs” Tina Mangla, Amit Sehgal, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, Vol.21, No.10, October 2006, pp. 1609-1619.
  11. “Modeling Aspects of sub-100nm MOSFETs for ULSI device applications”, Tina Mangla, Amit Sehgal, Mridula Gupta and R. S. Gupta, IEEE Transactions on Electron Devices Vol.54, No.1, Jan 2007, pp. 68-77.
  12. “Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, Thin Solid Films Vol.516, No.8, February 2008, pp. 2162-2170.
  13. “Poly–crystalline silicon thin film transistor: a two–dimensional threshold voltage analysis using Green’s function approach”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Technology and Science, Vol.7, No.4, December 2007, pp. 289-300.

 

International/Indian Conferences

Published

  1. “temperature dependent threshold voltage modeling of short geometry poly Si TFT”, Amit Sehgal, Tina Mangla, Mridula Gupta and R. S. Gupta, National Symposium on Advances in Microwaves and Lightwaves (NSMAL-2003), 13-14 October, University of Delhi, South Campus, New Delhi, India, 2003, pp. 116-119.
  2. “Temperature dependent electrical characteristics of short geometry Poly Si TFT for high frequency applications”, Amit Sehgal, Tina Mangla, Mridula Gupta and R. S. Gupta, National Conference on Radio Science in India (INCURSI – 2003), 27-29 November, National Physical Laboratory (NPL), New Delhi, India, 2003, p. 42.
  3. “Impact and Optimization of dielectric gate stack structure for MOSFETs design reliability”, Tina Mangla, Amit Sehgal, Mridula Gupta and R. S. Gupta, National Conference on Radio Science in India (INCURSI–2003), 27-29 November, National Physical Laboratory (NPL), New Delhi, India, 2003, p. 41.
  4. “Two dimensional analytical model of fully depleted poly-crystalline silicon thin film transistor”, Amit Sehgal, Tina Mangla, Mridula Gupta and R. S. Gupta, Thin Film Transistor Technologies VII Symposium, 2004 Joint International Meeting of ECS, 3-8 October, Honolulu, Hawaii, 2004.
  5. “Sub-threshold analysis for poly-silicon thin film transistor using Green’s function approach”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2004), 15–18 December, New Delhi, India, 2004, pp. 126-137.
  6. “Impact of gate stack architecture on MOSFETs including quantum mechanical effects”, Tina Mangla, Amit Sehgal, Mridula Gupta and R. S. Gupta, Asia Pacific Microwave Conference (APMC-2004), 15–18 December, New Delhi, India, 2004, pp. 189-190.
  7. “Enhancement in performance of poly-crystalline thin film transistors with gate dielectric and work-function”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, 3rd International Conference on Materials for Advanced Technologies, (ICMAT-2005), 3-8 July, Singapore, 2005, pp. 6-7.
  8. “Modeling and simulation of poly-crystalline silicon thin film transistor for improved gate transport efficiency”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, 10th International Symposium on Microwave and Optical Technologies (ISMOT-2005), 22-25 August, Fukuoka, Japan, 2005, pp. 410-413.
  9. “Poly-crystalline silicon thin film transistor: Modified Schottky gate contact for enhanced gate transport efficiency”, Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R. S. Gupta, XIII International Workshop on Physics of Semiconductor Devices (IWPSD-2005), 13-17 December, National Physical Laboratory (NPL), New Delhi, India, 2005, pp. 1040-1044.
  10. “Threshold voltage model for short-channel MOSFETs with quantum effects”, Tina Mangla, Amit Sehgal, Mridula Gupta and R. S. Gupta, XIII International Workshop on Physics of Semiconductor Devices (IWPSD-2005), 13-17 December, National Physical Laboratory (NPL), New Delhi, India, 2005, pp. 1030-1034.
  11. “Conventional Scaled Transformation Ratio: A failure to predict accurate device characteristics for sub-100nm gate stack MOSFETs”, R. S. Gupta, Tina Mangla, Amit Sehgal and Mridula Gupta, National Conference on Recent Advancements in Microwave Technique and Applications (Microwave-2006), 6-8 October, University of Rajasthan, Jaipur, 2006.
  12. “Improving the performance of poly-silicon thin film transistor for switching and driver circuitry”, Amit Sehgal, Tina Mangla, Mridula Gupta and R. S. Gupta, The 9th Asian Symposium on Information Display (ASID-2006), 8-12 October, Habitat World at Indian Habitat Centre, New Delhi, 2006, pp.400-403.
  13. “Physics Based Threshold Voltage Extraction And Simulation For Double-Gate Sub-100nm MOSFETs”, Amit Sehgal, Tina Mangla, Mridula Gupta, R. S. Gupta, 4th International Conference on Materials for Advanced Technologies, (ICMAT-2007), 1-6 July, Singapore, 2007, pp. 52.
  14. IEEE Sustainabbility Conference 2009, Computer Society Chapter, IEEE Delhi Section, held at HMR Institute of Technology and Management, Delhi, INDIA.
  15. “Sub 100nm Double Gate MOSFETs: A Study of Technological Defects and Carrier Quantization Effects”, Amit Sehgal, Ritesh Gupta, Mridula Gupta and R. S. Gupta, 12th International Symposium on Micorwave and Optical Technologies (ISMOT-2009), 16-19 December, Delhi, India, 2009.

 

Workshops

  1. Attended and successfully completed Electrawork 2009 workshop at Acharya Narendra Dev College, University of Delhi from June 01-12, 2009.
  2. Attended and successfully completed ICT Tier I Champions workshop at Institute of Lifelong Learning, University of Delhi from August 31 to September 11, 2009.
  3. Attended and successfully completed Integrating Multiple Technologies to Support Teaching and Learning Seminar cum Workshop at University of Delhi South Campus from September 24-26, 2009.
  4. Convener of the seminar organized in the college in the year 2008-2009.

5.    Resource Person for Tier II ILLL ICT Workshop at ILLL (For Administrative Staff), University Of Delhi.

6.    Resource Person for Tier II ILLL ICT Workshop at PGDAV (Eve.) College, University Of Delhi.

7.    Resource Person for Tier II ILLL ICT Workshop at Shivaji College, University of Delhi.

8.    Resource Person for Tier II ILLL ICT Workshop at S.G.T.B. Khalsa College, University of Delhi.

9.    Resource Person for Tier II ILLL ICT Workshop at Shyama Prasad Mukherjee College, University of Delhi.

10. Resource Person for Tier II ILLL ICT Workshop at Keshav Mahavidyalaya, University of Delhi.

11. Resource Person for Tier II ILLL ICT Workshop at Shaheed Bhagat Singh (Eve.) College, University Of Delhi.

12. Resource Person for Tier II ILLL ICT Workshop at Shri Guru Gobind Singh College of Commerce, University of Delhi.

13. Resource Person for Tier II ILLL ICT Workshop at Shyam Lal College, University of Delhi.

14. Resource Person for Tier II ILLL ICT Workshop at Indraprastha College for Women, University of Delhi.

  1. Attended And Successfully Completed Workshop on 3-D Animation and Design Visualization organized by MHRD, Govt. of India, Autodesk at Institute of Lifelong Learning, University Of Delhi from June 28 To July 02, 2010.
  2. Attended and successfully completed Mini-Colloquia on Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis at University of Delhi South Campus sponsored by IEEE Electron Device Society from March 14-15, 2012.
  3. Attended and successfully completed Science Academies Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates at University of Delhi South Campus sponsored by Indian National Sciency Academy (INSA) from February 17-18, 2012.
  4. Resource Person in Refresher Course in Information Technology at B. P. S. Mahila Vishwavidyalaya, Khanpur Kalan, Sonipat in May-June, 2012.
  5. Jury Member in INNOVATION IN SCIENCE PURSUIT FOR INSPIRED RESEARCH (INSPIRE) 2nd National Level Exhibition and Project Competition (NLEPC) at Delhi by Department of Science & Technology, Ministry of Science and Technology, Government of India from October 21-23, 2012.
  6. Jury Member in INNOVATION IN SCIENCE PURSUIT FOR INSPIRED RESEARCH (INSPIRE) 3rd National Level Exhibition and Project Competition (NLEPC) at Delhi by Department of Science & Technology, Ministry of Science and Technology, Government of India from October 8-10, 2013.
  7. Attended And Successfully Completed D-LITE Course conducted by Campus of Open Learning (COL), University of Delhi and Edinburgh College, UK at COL, Keshav Puram on November 18-21, 2013.
  8. Resource Person in Challenges in Physics Teaching and Evaluation at B. P. P. S. Teachers Training Centre, Pitampura, Delhi on 27 November, 2013.
  9. Resource Person in workshop Applications of LASER in Biotechnology at Hansraj College on December 16-17, 2013.