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Poly–crystalline silicon (poly–Si) materials started its journey with its applications in gate contacts, resistors and solar cells. But, in the past two decades, the scenario of poly–Si applications has completely changed. Now, poly–crystalline silicon thin film transistors (poly–Si TFTs) are upcoming devices in the field of device and IC applications. This has led to inclination of research interest towards improving its performance. In poly–Si TFTs, evaluation of the properties of grain–boundary trap states is of major importance for its development. The current trend towards down–scaling of device geometry has proved to be vital for this device; as the effect of grain–boundaries (such as high threshold voltage, low field–effect mobility etc.) present in the poly–Si film has been reduced. On the other hand, the appearance and the effect of grain–boundaries becomes distinct and thus cannot be worked out by simply using uniform distributed trap states as considered in the case of amorphous–Si. With this theory, together with the small geometry effects, this thesis effectively modeled the poly–Si TFT characteristics for better understanding of its performance on various geometries and bias parameters.

Chapter 1 framework is about the introduction of poly–Si TFTs. The chapter comprises of the historical background of the device. Further, the geometry of the device is described and a comparison of its geometry with conventional metal–oxide–silicon field–effect transistor (MOSFET) is done. The chapter progresses towards conduction phenomena in the poly–Si film and discusses about film properties. With the understanding of film behavior, the electrical characteristics of poly–Si TFT are discussed briefly.  The advantages of this poly–Si TFT over other devices are significant to be pointed out and are also described in the chapter. The demand of poly–Si TFT has resulted in new structures to boost its performance. From experimental point of view, some often used structures; its fabrication techniques and fabrication based device performances have also been highlighted in the introductory chapter 1.

To analyze poly–Si film/TFT merits over its counterparts; a comparative study of its applications and classification according to its feature size is done. Based on the growing interest in the field of applications, some circuits implementing poly–Si TFTs have been explained. With its developing research interest, some up–coming device substrates and device structures worked out using these novel substrates are also described briefly. The last sections encompass different modeling techniques, need of modeling, emphasis on analytical modeling and scope of work done in the thesis.   

In Chapter 2, a temperature dependent quasi two–dimensional (2–D) analytical model has been developed for short geometry poly–Si TFTs. The 2–D modeling comes into existence, as the device dimensions roll–down; one–dimensional (1–D) modeling fails to predict correct characteristics of the device under consideration. Apart from 2–D analysis, several secondary and parasitic effects namely short–channel effects (SCEs), drain–induced barrier lowering (DIBL) effect, inverse narrow width effect, and fringing field effect become considerable and play a pivotal role in altering the device performance. Also, poly–Si TFTs differ from their crystalline silicon counterparts due to the grain–boundaries and intra–grain defects present in the poly–Si film, which introduce many significant differences such as low field mobility dependence on gate bias, high series resistance, high leakage current, high turn–on voltage due to intra–grain–boundary defects and low breakdown voltage. A successful design of such circuits requires a proper understanding of the electrical properties of poly–Si TFTs.

Thermal effect has been one of the unavoidable effects, which causes instability in the device characteristics. But, the semiconductor devices are meant to operate for many applications under different temperature conditions, such as in IC technology the chips must exhibit good device performance under given temperature ranges. Thus, it is needed to formulate a model, which takes into account the drift in the performance of device characteristics due to change in temperature together with above mentioned secondary and parasitic effects to predict the characteristics accurately.

The analysis involved in chapter 2 comprises of threshold voltage formulation for various device parameters. Also, the mobility expression meant for poly–Si TFT is modified and modeled with dependence on device parameters and is discussed in this chapter. Based on the developed temperature dependent threshold voltage and field–effect mobility model, the current–voltage characteristics and transconductance are obtained. The cut–off frequency which is an important figure of merit for microwave solid state devices and determines the device switching speed, has also been modeled. The effect of fringing capacitance in limiting the cut–off frequency, when the device dimensions are scaled down to the sub–micrometer region has also been considered.

Thus, the combined effect of all temperature dependent parameters together with the effect of grain size, trapped charges and channel dimensions etc. on device characteristics (transfer characteristics, cut–off frequency) is studied in this work. From our analysis, the maximum transconductance obtained are 6.72µS, 4.09µS and 2.78µS and cut–off frequency are 5.23GHz, 3.18GHz and 2.16GHz corresponding to device dimensions 0.5µm and 5.7µS, 3.14µS and 2.03µS and 0.83GHz, 0.46GHz and 0.29GHz for 2.0µm device dimensions at V_d = 1.0V at temperatures 218 K, 300 K and 398 K respectively. The close proximity with experimental results shows the validity of our model.

Chapter 3 describes about the prevalent floating–body effects in the poly–Si TFTs, which are triggered by impact–ionization charging of the film body, commonly known as the ‘kink’ effect. This kink effect is not harmful but is undesirable because of the abnormality it creates, which can be detrimental in CMOS circuits for analog and digital applications, memories and displays. It causes current overshoots in the devices, thus is difficult to model and also to implement in circuit simulators, and therefore must be constrained. The kink effect shows its maximum impact at the gate voltage somewhat lower than the drain voltage, because the generation rate of holes induced by the avalanche process shows its maximum at this condition (drain voltage > gate voltage). It has been observed by many researchers that avalanche generation effects are much larger in the poly–Si TFTs than in single–crystal devices. Poly–silicon devices show much larger avalanche effects because the space charge is primarily determined by trapped carriers and not by free carriers. These traps occur due to the presence of grain–boundaries in the poly–Si film.

Thus, an effective analytical model for the kink regime of a short–channel poly–Si TFT is presented in chapter 3. The modeled results were found to be in good agreement with the available experimental results. The work is based on the impact–ionization phenomenon that occurs due to the generation of high electric fields near the drain. Expressions for the channel potential, avalanche multiplication factor and kink current are developed. Since short–channel and grain–boundary effects are seen to be more pronounced at short–channel lengths, thus analysis also incorporates their effect in the expressions developed. The impact of smaller dimensions and variation in grain size is also discussed. The results show that the kink effect is more prominent at smaller dimensions and smaller grain size. The work also depicts the dependence of the kink current on various applied biases. The model developed is coupled with the model for linear regime of a short–channel poly–Si TFT, and produces therefore a model valid for all regions of device.

Chapter 4 outlook is about a two–dimensional (2–D) model for a poly–Si TFT. In the previous chapters, a quasi two–dimensional approach was adopted to solve the Poisson’s equation. The quasi two–dimensional treatment was predicting good results, but lacks by several factors: (i) the SCEs and DIBL effect were incorporated in the modeling by explicitly introducing expressions/parameters to incorporate their effect, (ii) the modeling does not account for the individual contribution of grain–boundaries present in the channel and (iii) the traps chosen were of uniform distribution throughout the film. Keeping in view these shortcomings, this chapter encompasses the 2–D analysis based on potential distribution of the device under the depletion approximation for poly–Si TFTs. Green’s function approach is found to be a promising approach to solve the 2–D Poisson’s equation for any arbitrary doping profile. The developed model gives insight into device behavior due to the effects of traps and grain–boundaries. The figures demonstrate the effect of the number of grain–boundaries present in the channel. SCEs and DIBL effects can also be seen from the figures in chapter 4 and as device dimensions are reduced, these effects contribute in minimizing of potential barrier generated due to traps at the grain–boundary. The drain bias also affects the channel potential as it overcomes the barriers found close to the drain–end. The transfer characteristics are analyzed for various channel length and drain biases. The maximum transconductance and cut–off frequency achieved is 30µS and 52.7GHz at channel length equal to 0.4µm and V_d=0.25V. This value of cut–off frequency forms basis to find its applicability for microwave frequency applications. The results obtained show a good agreement with simulated results and with numerical model based on nine–point finite difference method together with same set of boundary conditions and space charge density distribution, thus justifying our analysis.

To overcome the high threshold voltage demerit of poly–Si TFTs, Chapter 5 focuses on 2–D analysis for double–gate (DG) poly–Si TFTs. It is concluded from the formulation that the targeted threshold voltage depends upon the physical gate dielectric thickness, dielectric constant, substrate doping concentration, grain size, and drain voltage. The scope of enhancement in device threshold voltage roll–off with these parameters is observed and further its variation with various parameters is studied. If the poly–Si film thickness is greater than the maximum depletion width induced by horizontal and lateral electric fields, then simultaneously two channels will grow independently depending upon acting parameters. On the other hand, if the film thickness is less than or equal to total depletion width, volume inversion of carriers will occur. The developed formulation incorporates the effects due to traps, grain–boundaries, SCEs and DIBL effect, and can be inferred from the characteristics. A comparison of DG TFT device characteristics with SG TFT characteristics is analyzed, and enhancement of device performance is seen on application of the bottom gate. The addition of the bottom gate have greatly reduced the threshold voltage and increased the drain current performance, and in–turn proving a better choice for integrated circuits with switching and drive circuit performance. The results obtained show an excellent agreement with numerical modeling based on the finite difference method and good agreement with simulation results, thus demonstrating the validity of our model.

Multi–material gate (MMG) poly–Si TFTs, a new aspect to work upon, for controlling the lateral electric field and grain–boundary effect is presented in Chapter 6. The developed formulation incorporates the effects due to traps and grain–boundaries. SCEs and DIBL effect are also accosted in the analysis. The work done proved to be good choice over FOLD and GOLDD structures, as the reduction of DIBL effect and grain–boundary effect (reduction in potential barriers) is achieved without increasing the device resistivity by employing gate–engineered structures. It is observed from the analysis that by employing optimized set of device parameters and biases for the gate–engineered structures, one can shift the minima position even at high drain voltages at a position equal to 0.5L, the conventional position for evaluation of threshold voltage at low drain biases. Thus, one can achieve a symmetric channel potential profile from an asymmetric structure with the help of proper set of parameters (geometry and bias). The results obtained show a good agreement with simulated results, thus demonstrating the validity of our model. Although, the introduction of MMG proves to be a good choice to overcome DIBL effect and grain–boundary effect (suppression of potential barrier), but the values of gate material work–function and its dimensions needs to be optimized in accordance to practical device applicability.

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