Journal of Semiconductor Technology and Science, Vol.4, No.3, September 2004, pp. 228-239.

• Optimization of Gate Stack MOSFETs with Quantization Effects

  Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta

   Abstract—In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of high-k dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and ID-VD characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

  

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Solid State Electronics, Vol.49, No.3, March 2005, pp. 301-309.

• Temperature dependence on electrical characteristics of short geometry poly-crystalline silicon thin film transistor

  Amit Sehgal, Tina Mangla, Mridula Gupta, R. S. Gupta

  Abstract—In the present paper a temperature dependent analytical model for poly-crystalline silicon TFT incorporating the short channel effects and inverse narrow width effects is developed. The temperature dependent modeling parameters and the effect of fringing capacitances are considered to evaluate the drain current, transconductance and cut-off frequency etc. The effect of change in mobility with gate voltage has also been incorporated and the results so obtained show excellent match with the experimental results thus proving the validity of our model.

  

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IEEE Transactions on Microwave Theory and Techniques, Vol.53, No. 9, September 2005, pp. 2682-2687.

• Sub-Threshold Analysis and Drain Current Modeling of Polysilicon Thin-Film Transistor Using Green’s Function Approach

  Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta, and R. S. Gupta

  Abstract—An analytical analysis for a poly-crystalline silicon thin-film transistor is presented. The Green’s function approach is adopted to solve the two-dimensional Poisson’s equation using Neumann’s boundary conditions at the silicon–silicon di-oxide interface. The developed model gives an insight of device behavior due to the effect of traps and also grain–boundary effect. The analysis of threshold voltage depicts short-channel effects and drain-induced barrier lowering. The model is extended to analyze the transfer characteristics and obtain the transconductance of the device. The results obtained show good agreement with the numerical model and with simulated results, thus proving the validity of our model.

  

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Journal of Semiconductor Technology and Science, Vol.5, No.3, September 2005, pp. 159-167.

• Physics-based Algorithm Implementation for Characterization of Gate-dielectric Engineered MOSFETs including Quantization Effects

  Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta

  Abstract—Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and polydepletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by selfconsistent solution of the Schrödinger and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

  

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Semconductor Science and Technology, Vol.21, March 2006, pp.370-377.

• Physics based threshold voltage extraction and simulation for poly-crystalline thin film transistors using a double-gate structure

   Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta and R S Gupta 

  Abstract—In this work, a two-dimensional potential distribution formulation/model is presented for double-gate poly-crystalline silicon thin film transistors. The work aims at deriving a potential solution for the threshold voltage estimation of the device under consideration. The Green’s function approach is adopted for the two-dimensional potential solution. The developed formulation incorporates the effects due to traps and grain boundaries. The existence of short-channel effects and drain-induced barrier-lowering effects can also be seen from the characteristics. A relation to achieve the targeted threshold voltage with the physical gate dielectric thickness, dielectric constant, substrate doping concentration, grain size and drain–source voltage as parameters is also presented. The model is then extended to evaluate drain current performance. The results obtained show an excellent agreement with numerical modelling based on the finite difference method and also a good agreement with simulation results, thus demonstrating the validity of our model.

  

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Thin Solid Films, Vo1.54, No.1-2, May 2006, pp. 55-58.

• Enhancement in performance of poly-crystalline thin film transistors with gate dielectric and work-function 

  Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta, R.S. Gupta

  Abstract—In this article, a double gate poly-Si TFT structure is analyzed to study the variation of channel potential profile and threshold voltage with dielectric constant, metal work-function and other device parameters. Green’s Function is used to obtain two-dimensional potential distribution. The potential profiles obtained give insight into the device behavior and an estimation of threshold voltage for the device under consideration. Device simulation is also done using ATLAS simulator and the results obtained are compared with proposed two-dimensional model. The modeled results are found to be in good agreement with simulated data.

  

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International Journal of Electronics, Vol.93, No.5, May 2006, pp. 279-289.

• Analytical modelling of the kink regime of a short channel polycrystalline silicon thin film transistor

  Sonia Chopra, Amit Sehgal and R. S. Gupta

  Abstract—An analytical model for the post-saturation region including the kink regime of a short channel polycrystalline silicon thin film transistor is presented. Considering the impact ionization mechanism caused by high electric field in the pinch off region near the drain, an expression for the channel potential is developed. The avalanche multiplication factor, an important parameter monitoring the impact ionization phenomenon is determined and discussed. Further, an expression for the drain-source current in the kink regime is determined and studied. The dependence of the kink current on the channel length and grain size is investigated. The results so obtained are compared with experimental data and an excellent match verifies the proposed model.

  

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International Journal on Microwave and Optical Technologies, Vol.1, No.2, August 2006, pp. 411-416.

• Modeling and Simulation of Poly-crystalline Silicon Thin Film Transistor for Improved Gate Transport Efficiency

  Amit Sehgal, Tina Mangla, Sonia Chopra, Mridula Gupta, R. S. Gupta

  Abstract—In this work, a two-dimensional potential distribution formulation/model is presented for modified Schottky gate contact poly-crystalline silicon thin film transistors. The work aims at deriving potential solution and in this way trying to limit the impact of punch-through condition. Green’s function approach is adopted for the two-dimensional potential solution. The developed formulation incorporates the effects due to traps, grain-boundaries, short-channel and drain-induced barrier lowering (DIBL). The results obtained show good agreement with simulation results, thus demonstrating the validity of our model.

  

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International Journal on Microwave and Optical Technologies, Vol.1, No.1, June 2006, pp. 106-113.

• Enhancement in Performance of sub-100nm MOSFETs With Gate Stack Architecture

  Tina Mangla, Amit Sehgal, Mridula Gupta, R. S. Gupta

   Abstract—A 2-D analysis for different gate stack dielectric structured MOSFETs with carrier quantization effects is presented using Green’s function for solving Poisson’s equation. Explicit results for potential distribution, threshold voltage and drain current are presented. Based on extensive simulation and developed formulation, it is found that using double-layer gate stack structures with low-k dielectric as spacer material can well confine the electric fields within the channel. Comparison of the results thus obtained is done with simulated results to justify the analysis.

  

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IEEE Transactions on Electron Devices, Vol.54, No.1, Jan 2007, pp. 68-77.

• Modeling Aspects of Sub-100-nm MOSFETs for ULSI-Device Applications

  Tina Mangla, Amit Sehgal, Mridula Gupta, and R. S. Gupta

  Abstract—Ultrathin oxides (1–3 nm) are foreseen to be used as gate dielectric in complementary-MOS technology during the next ten years. Nevertheless, they require new approaches in modeling and characterization due to the onset of quantum effects. Predicting device characteristics including quantum effects requires solving of Schrödinger’s equation together with Poisson’s equation. In this paper, Poisson’s equation is solved in two dimensions (2-D) over the entire device using Green’s function approach, while Schrödinger’s equation is decoupled using triangular potential-well approximation. The carrier density thus obtained is included in the space-charge density of Poisson’s equation to obtain quantum-carrier confinement effects in the modeling of sub-100-nm MOSFETs. The framework also consists of the effects of source/drain-junction curvature and depth, short-channel effects, and drain-induced barrier-lowering effect. The 2-D potential profiles thus obtained with above said effects form the basis for an estimation of threshold voltage. Using this potential distribution, the transfer characteristics of the device are also evaluated. The method presented is comprehensive in the treatment, as it neither requires self-consistent numerical modeling nor it contain any empirical or fitting expression/parameter to provide formulation for quantized-carrier effect in the inversion layer of MOSFETs. The results obtained show good agreement with available results in the literature and with simulated results, thus proving the validity of our model.

  

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Semiconductor Science and Technology, Vol.21, No.10, October 2006, pp. 1609-1619.

• Modelling challenges in sub-100 nm gate stack MOSFETs

  Tina Mangla, Amit Sehgal, Mridula Gupta and R S Gupta

  Abstract—The aim of this work is to present a two-dimensional analysis for different gate stack dielectric structured n-MOSFETs with carrier quantization effects. The model is developed using Green’s function for solving Poisson’s equation, without implying the extensive effort required for a fully self-consistent solution of the Schrödinger and Poisson equations. Explicit results for potential distribution, threshold voltage and drain current, with different structural and bias parameters, have been presented, typical in the operation of modern devices. The model includes short channel, drain bias, and junction curvature effects. Based on extensive simulation and developed formulation, it is found that the conventional concept of a scaled transformation method for gate stack structures to replace silicon-dioxide (SiO2) dielectric thickness with a thicker high dielectric does not predict the same characteristics. It has also been shown that using double-layer gate stack structures with low-k dielectric as the spacer material can well confine the electric fields within the channel, thereby enhancing gate controllability on the channel charge. Comparison of the results thus obtained is done with simulated results to justify the analysis.

  

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Thin Solid Films, Vol.516, No.8, February 2008, pp. 2162-2170.

• Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency 

  Amit Sehgal, Tina Mangla, Mridula Gupta, R.S. Gupta

  Abstract—In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects (SCEs) and drain-induced barrier lowering (DIBL) effect exists and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and improve the carrier transport efficiency.  Green’s function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus demonstrating the validity of our model.

  

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Journal of Semiconductor Technology and Science, Vol.7, No.4, December 2007, pp. 289-300.

• Poly-crystalline Silicon Thin Film Transistor: a Two dimensional Threshold Voltage Analysis using Green's Function Approach

  Amit Sehgal, Tina Mangla, Mridula Gupta, and R. S. Gupta

  Abstract—A two–dimensional treatment of the potential distribution under the depletion approximation is presented for poly–crystalline silicon thin film transistors. Green’s function approach is adopted to solve the two–dimensional Poisson’s equation. The solution for the potential distribution is derived using Neumann’s boundary condition at the silicon–silicon di–oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain–boundaries. Also short–channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

  

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